Today, packing dies within integrated circuits is common knowledge. By packing different dies within one single mold, a package may provide increased functionality. It may also be possible to pack different application specific integrated circuits (ASIC) into one single mold cap to provide different functionality within one chip.
For instance, a main digital baseband application specific integrated circuit (ASIC) for high speed data packet access (HSDPA) and a protocol specific digital modem ASIC may be stacked on top of each other within single package. The integration within a single package allows providing HSDPA functionality by one single device.
Stacked chip scale packages (stacked CSP) with two or more dies stacked within a single package assembly are known. These stacked packages may be organic packages, which are wirebonded and overmolded in a chip scale package profile. Typical ball pitch ranges from 0.5 to 0.8 mm for these packages. Also ball grid arrays using full-sized balls with only 0.5 mm maximum height are known. These chips are used in surface down configuration. The printed circuit board (PCB) may be connected to these chips through wirebonding.
However, as there is a need to reduce the baseband area of chips, further size reduction, in particular in terms of chip area, is necessary.